Process corners may vary amongst wafers from which integrated circuit (IC) dies are cut, amongst IC dies cut from the same wafer, and/or within a particular one of the IC dies. Process corner variations may adversely impact timing and/or other characteristics of an IC.
In an IC die that includes multiple discernible IC blocks, such as in a system-on-a-chip (SoC), an IC block may be adversely impacted by random variations caused by other IC blocks.
Compensation for process corner variations and/or other random variations may be provided with an on-die programmable fuse array, programmed based on results of a high volume manufacturing (HVM) tests. A fuse array may necessitate additional pins for addressing, and may necessitate a special addressing scheme to accommodate security concerns.
Compensation for process corner variations and/or other random variations may also be provided with an on-die trim or calibration system.
Programmed fuse data may not be available until after commencement of a boot sequence. Similarly, data from an on-die trim or calibration system may not be available for some time following power-up. Where process adjustment compensation is desired upon activation or power-up (i.e., at time-zero), an IC die or IC block may be over-designed to avoid adverse impacts of process variations and/or other random variations.
In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears.